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Design of adiabatic two＇s complement multiplier-accumulator based on CTGAL

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摘要我们基于clocked传播门为一个布思编码器建议一个新式样计划断热的逻辑(CTGAL)。当时，在新式样，布思编码器的结构的复杂性被减少速度更多样地被改进。断热二是补充收益增殖率,乘法器,乘数蓄电池(MAC)而且一个图案基于CTGAL。计算机模拟结果显示设计电路让正确逻辑工作并且显著地与MAC的相比的更少的能源消耗基于互补金属氧化物半导体(互补金属氧化物半导体)逻辑。

DOI zdlo2z5zdl/668240

作者 Peng-jun WANG;Jian XU;Shi-yan YING

机构地区不详

出处《浙江大学学报：A卷英文版》 2009年2期

关键词传输门绝热逻辑电路乘法器-累加器 BOOTH算法补码

分类 [理学][物理]

出版日期 2009年02月12日（中国期刊网平台首次上网日期，不代表论文的发表时间）

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浙江大学学报：A卷英文版

浙江大学学报：A卷英文版

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传输门绝热逻辑电路乘法器-累加器 BOOTH算法补码

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