简介：期刊极化调制方案被建议压制预定在solitons的二个极化部件之间的频率变化导致的极度紧张。Inperiodical极化调制方案，soliton的极化状态被调制为压制同等地激动预定二个不相等的极化部件在套住的thesoliton导致的极度紧张。而且，极化调整能在每个继电器远处削弱随机的birefringence在soliton脉搏的效果。数值结果证明预定极度紧张的soliton被我们的建议方法压制。

简介：Thispaperpresentsaschemetoidentifyandcompensatethetimingmismatchesbetweentwochannelsfortimeinterleavedphotonicanalog-to-digitalconverters(TIPADCs).Theimpactofelectro-opticsamplingisremovedbypreprocessingfirstly.ThenacalibrationmethodcombiningchoppingprocessingandaHilberttransformisproposedtoidentifythetimingmismatches,whichcanbefurthercompensatedbyusingvariousmaturecompensationalgorithms.Theprincipleoftheproposedmethodisderivedtheoretically.Theperformanceoftheschemeisanalyzedbysimulation.Theresultsshowthattheharmonicinducedbytimingmismatchescanbesuppressedbymorethan30dBusingtheproposedcorrectionscheme.

简介：Withtheincreaseoftheclockfrequencyandsiliconintegration,powerawarecomputinghasbecomeacriticalconcerninthedesignoftheembeddedprocessorandsystem-on-chip(SoC).Dynamicvoltagescaling(DVS)isaneffectivemethodforlow-powerdesigns.However,traditionalDVSmethodshavetwodeficiencies.First,theyhaveaconservativesafetymarginwhichisnotnecessaryformostofthetime.Second,theyareexclusivelyconcernedwiththecriticalstageandignorethesignificantpotentialfreeslacktimeofthenoncriticalstage.Thesefactorsleadtoalargeamountofpowerwaste.Inthispaper,anovelpipelinestructurewithultra-lowpowerconsumptionisproposed.Itcutsoffthesafetymarginandtakesuseofthenoncriticalstagesatthesametime.Aprototypepipelineisdesignedin0.13mtechnologyandanalyzed.Theresultshowsthatalargeamountofenergycanbesavedbyusingthisstructure.Comparedwiththefixedvoltagecase,50%oftheenergycanbesaved,andwithrespecttothetraditionaladaptivevoltagescalingdesign,37.8%oftheenergycanbesaved.