简介：Thispaperdescribesamaximumtimedifferencepipelinedarithmeticchip,the36-bitadderandsubtractorbasedon1.5μmCMOSgatearray.Thechipcanoperateat60MHz,andconsumeslessthan0.5Watt.Theresultsarealsostudied,andamoreprecisemodelofdelaytimedifferenceisproposed.
A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array
